Email: fd@francescodellanna.xyz - Phones: 0039 3337733771, 0047 47722385
Git: https://gitlab.com/francescodellanna
Website: https://francescodellanna.xyz
Technical Strengths
Programming languages - VHDL, Verilog, C, Posix Shell, Python, Octave
Revision control tools - GIT, SVN
Industrial Experience
2021 - Current : Digital Designer at Kongsberg
I have been actively involved in the design and development of FPGA solutions for mapping, fishery and naval sonars, some of the projects worked on are EM2042, SY50, SD9500, HISAS.
2019 - 2021 : Digital Designer at Sony
I contributed in the design and development of ASIC circuits for automotive image sensor. I am the inventor of a novel image compression algorithm US11678085B2, US2022159207A1. I worked on a temperature and power interface module for IMX728 ISX728 image sensors.
2017 - 2019 : Digital Designer at Omnivision Technology
I contributed in the design, development and test of ASIC circuits for automotive image sensors (OX8a OX8b Ox3c). I have been actively involved in multiple modules comprising the input and output data-paths, as well as built-in tests (Watchdog, PMBIST, SBIST).
Academical Research
2016 - 2018 : CTBU and USN Researcher
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IC design for a piezoelectric harvesting interface based on a frequency up-conversion technique.
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Design of a synthesis tool for preliminary topology identification of a low-power voltage multiplier.
Granted projects
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Chongqing Key Laboratory of Micro-Nanosystems Technology and Smart Transducing no. KFJJ2017087.
List of publications
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Francesco Dell' Anna, Tao Dong, Ping Li, Wen Yumei, Zhaochu Yang, Mario R. Casu, Mehdi Azadmehr and Yngvar Berg, State-of-the-art power management circuits for piezoelectric energy harvesters. IEEE Circuits and Systems Magazine, DOI: 10.1109.
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Francesco Dell' Anna, Tao Dong, Ping Li, Wen Yumei, Mehdi Azadmehr, Mario R. Casu and Yngvar Berg, Lower-order compensation chain threshold-reduction technique for multi-stage voltage multipliers., Sensors, DOI:10.3390.
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Francesco G. Dell Anna, Tao Dong, Ping Li, Wen Yumei, Mehdi Azadmehr and Yngvar Berg Low-power voltage multiplier synthesis tool for preliminary topology identification., Conference in IEEE ICOSST, DOI: 10.1109.
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Anup Das, Yuefeng Wu, Khanh Huynh, Francesco Dell Anna, Francky Catthoor and Siebren Schaafsma, ”Mapping of Local and Global Synapses on Spiking Neuromorphic Hardware”, Conference on Design Automation and Test in Europe, DOI: 10.23919.
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Wenjun Lin, Xuefu Xu, Francesco DellAnna, ”The impact of economic plans on the Chinese education system: a machine learning approach”, DOI: 10.3280 CADMO.
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Adarsha Balaji, Anup Das, Yuefeng Wu, Khanh Huynh, Francesco DellAnna, Giacomo Indiveri, Jeff Krichmar, Nikil Dutt, Siebren Schaafsma, and Francky Catthoor, ”Mapping Spiking Neural Networks on Neuromorphic Hardware”, IEEE Transactions on Very Large Scale Integration 2019, DOI: 10.1109.
Education
2015 - 2016 : IMEC Master Thesis
Interface between RTL and application neuromorphic simulator.
2015 - 2016 : KULeuven Electronics and Integrated Circuits
Power and propagation delay estimation in digital circuits, hardware software co-design.
2014 - 2016 : Master in Embedded Systems
Fundamental knowledge in embedded systems both software and hardware, digital design and processor architectures.
2011 - 2013 : Bachelor in Embedded Systems
Fundamental knowledge in computer architectures and algorithms.
Few words about me
I am a digital circuit designer who wants to share my personal experience and views on technical problems.
I am originally from Italy but thanks to my profession and studies I had the opportunity to live in Belgium, China and I am currently in Norway.